Abstract
Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-hard problem. In this paper, a memetic algorithm (MA) for a nonslicing and hard-module VLSI floorplanning problem is presented. This MA is a hybrid genetic algorithm that uses an effective genetic search method to explore the search space and an efficient local search method to exploit information in the search region. The exploration and exploitation are balanced by a novel bias search strategy. The MA has been implemented and tested on popular benchmark problems. Experimental results show that the MA can quickly produce optimal or nearly optimal solutions for all the tested benchmark problems. © 2007 IEEE.
| Original language | English |
|---|---|
| Pages (from-to) | 62-69 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics |
| Volume | 37 |
| Issue number | 1 |
| Early online date | 23 Jan 2007 |
| DOIs | |
| Publication status | Published - Feb 2007 |
| Externally published | Yes |
Bibliographical note
This work was supported in part by the National Natural Science Foundation of China under Grant 60428202. This paper was recommended by Guest Editor Y. S. Ong.Keywords
- Floorplanning
- Genetic algorithm (GA)
- Local search
- Memetic algorithm (MA)
- Very large scale integrated circuit (VLSI)