A realizable architecture for genetic algorithm parallelism

K. S. TANG; K. F. MAN; Y. C. HO; S. KWONG

doi:10.1016/S0967-0661(98)00077-X

A realizable architecture for genetic algorithm parallelism

K. S. TANG, K. F. MAN, Y. C. HO, S. KWONG

Research output: Journal Publications › Journal Article (refereed) › peer-review

9 Citations (Scopus)

Abstract

A novel hardware architecture is specifically designed here to fulfil the realization of parallelism of genetic algorithms. It is a modular structure which consists of three individual processing units, namely the Genetic Operator, the Fitness Evaluator and the Objective Function Sequencer. Each unit is implemented by the use of an FPGA chip. Due to its modular structure, this design possesses a unique flexible and scalable feature that is capable of handling various engineering applications. Such a scalable feature can markedly improve the computing speed of this hardware simply by the increase in the fitness evaluators. The results obtained are very encouraging for future development, particularly where genetic algorithms are used in real-time system applications. © 1998 Published by Elsevier Science Ltd. All rights reserved.

Original language	English
Pages (from-to)	897-903
Journal	Control Engineering Practice
Volume	6
Issue number	7
DOIs	https://doi.org/10.1016/S0967-0661(98)00077-X
Publication status	Published - Jul 1998
Externally published	Yes

Keywords

Filter design
Genetic algorithms
Hardware architectures
Parallelism

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10.1016/S0967-0661(98)00077-X

Cite this

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title = "A realizable architecture for genetic algorithm parallelism",

abstract = "A novel hardware architecture is specifically designed here to fulfil the realization of parallelism of genetic algorithms. It is a modular structure which consists of three individual processing units, namely the Genetic Operator, the Fitness Evaluator and the Objective Function Sequencer. Each unit is implemented by the use of an FPGA chip. Due to its modular structure, this design possesses a unique flexible and scalable feature that is capable of handling various engineering applications. Such a scalable feature can markedly improve the computing speed of this hardware simply by the increase in the fitness evaluators. The results obtained are very encouraging for future development, particularly where genetic algorithms are used in real-time system applications. {\textcopyright} 1998 Published by Elsevier Science Ltd. All rights reserved.",

keywords = "Filter design, Genetic algorithms, Hardware architectures, Parallelism",

author = "TANG, {K. S.} and MAN, {K. F.} and HO, {Y. C.} and S. KWONG",

year = "1998",

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AB - A novel hardware architecture is specifically designed here to fulfil the realization of parallelism of genetic algorithms. It is a modular structure which consists of three individual processing units, namely the Genetic Operator, the Fitness Evaluator and the Objective Function Sequencer. Each unit is implemented by the use of an FPGA chip. Due to its modular structure, this design possesses a unique flexible and scalable feature that is capable of handling various engineering applications. Such a scalable feature can markedly improve the computing speed of this hardware simply by the increase in the fitness evaluators. The results obtained are very encouraging for future development, particularly where genetic algorithms are used in real-time system applications. © 1998 Published by Elsevier Science Ltd. All rights reserved.

KW - Filter design

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KW - Hardware architectures

KW - Parallelism

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DO - 10.1016/S0967-0661(98)00077-X

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VL - 6

SP - 897

EP - 903

JO - Control Engineering Practice

JF - Control Engineering Practice

IS - 7

ER -

A realizable architecture for genetic algorithm parallelism

Abstract

Keywords

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