A VLSI design for a real-time video decoder

Y. K. CHAN; S. KWONG; K. L. CHAN; T. F. WONG

doi:10.1109/VLSISP.1995.527517

A VLSI design for a real-time video decoder

Y. K. CHAN, S. KWONG, K. L. CHAN, T. F. WONG

Research output: Book Chapters | Papers in Conference Proceedings › Conference paper (refereed) › Research › peer-review

Abstract

This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a Signal-to-noise ratio of 32 dB. It is found that the real-time decoder has a better performance when compared with [2,3,4]. The static decompression part of the decoder is based on the SDIC algorithm. The major advantage of the SDIC algorithm is the hardware simplicity and its VLSI realization. In this paper, the hardware design of the real-time decoder and results will be presented.

Original language	English
Title of host publication	IEEE Workshop on VLSI Signal Processing, Proceedings
Publisher	IEEE
Pages	461-469
Number of pages	9
ISBN (Print)	0780326121
DOIs	https://doi.org/10.1109/VLSISP.1995.527517
Publication status	Published - Oct 1995
Externally published	Yes
Event	1995 IEEE Workshop on VLSI Signal Processing - Rihga Royal Hotel, Sakai, Japan Duration: 16 Oct 1995 → 18 Oct 1995

Workshop

Workshop	1995 IEEE Workshop on VLSI Signal Processing
Country/Territory	Japan
City	Sakai
Period	16/10/95 → 18/10/95

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10.1109/VLSISP.1995.527517

Cite this

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title = "A VLSI design for a real-time video decoder",

abstract = "This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a Signal-to-noise ratio of 32 dB. It is found that the real-time decoder has a better performance when compared with [2,3,4]. The static decompression part of the decoder is based on the SDIC algorithm. The major advantage of the SDIC algorithm is the hardware simplicity and its VLSI realization. In this paper, the hardware design of the real-time decoder and results will be presented.",

author = "CHAN, {Y. K.} and S. KWONG and CHAN, {K. L.} and WONG, {T. F.}",

year = "1995",

month = oct,

doi = "10.1109/VLSISP.1995.527517",

language = "English",

isbn = "0780326121",

pages = "461--469",

booktitle = "IEEE Workshop on VLSI Signal Processing, Proceedings",

publisher = "IEEE",

note = "1995 IEEE Workshop on VLSI Signal Processing ; Conference date: 16-10-1995 Through 18-10-1995",

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AU - KWONG, S.

AU - CHAN, K. L.

AU - WONG, T. F.

PY - 1995/10

Y1 - 1995/10

N2 - This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a Signal-to-noise ratio of 32 dB. It is found that the real-time decoder has a better performance when compared with [2,3,4]. The static decompression part of the decoder is based on the SDIC algorithm. The major advantage of the SDIC algorithm is the hardware simplicity and its VLSI realization. In this paper, the hardware design of the real-time decoder and results will be presented.

AB - This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a Signal-to-noise ratio of 32 dB. It is found that the real-time decoder has a better performance when compared with [2,3,4]. The static decompression part of the decoder is based on the SDIC algorithm. The major advantage of the SDIC algorithm is the hardware simplicity and its VLSI realization. In this paper, the hardware design of the real-time decoder and results will be presented.

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U2 - 10.1109/VLSISP.1995.527517

DO - 10.1109/VLSISP.1995.527517

M3 - Conference paper (refereed)

SN - 0780326121

SP - 461

EP - 469

BT - IEEE Workshop on VLSI Signal Processing, Proceedings

PB - IEEE

T2 - 1995 IEEE Workshop on VLSI Signal Processing

Y2 - 16 October 1995 through 18 October 1995

ER -

A VLSI design for a real-time video decoder

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