Formal verification of fault-tolerant software design : the CSP approach

Wing Lok YEUNG, S. A. SCHNEIDER

Research output: Journal PublicationsJournal Article (refereed)peer-review

6 Citations (Scopus)

Abstract

Software design techniques for tolerating both hardware and software faults have been developed over the past few decades. Paradoxically, it is essential that fault-tolerant software is designed with the highest possible rigour to prevent faults in itself. Such rigour is provided by formal methods and aided by model checking. We illustrate an approach to fault-tolerant software design based on communicating sequential processes through a running example.
Original languageEnglish
Pages (from-to)197-209
Number of pages13
JournalMicroprocessors and Microsystems
Volume29
Issue number5
DOIs
Publication statusPublished - 1 Jun 2005

Keywords

  • Fault tolerance
  • Formal verification
  • Model checking
  • Software design

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