Tnvmalloc: A Thread-Level-Based Wear-Aware Allocator for Nonvolatile Main Memory

Chunhua XIAO, Lin ZHANG, Mingliang ZHOU*

*Corresponding author for this work

Research output: Journal PublicationsJournal Article (refereed)peer-review

Abstract

The nonvolatile main memory (NVMM) has the advantages of near-DRAM speed, byte-Addressability, and persistence, and presents limitations in write durability. The memory allocator, a fundamental data structure of memory management, can effectively mitigate the wear speed, thereby prolonging the NVMM lifetime. Nevertheless, balancing the performance and writing reliability in single and multi-Thread scenarios is still an open problem for NVMM allocators. In this paper, we propose a thread-level wear-Aware allocator (Tnvmalloc) that divides the NVMM space into multiple management granularities and then dynamically selects the optimal blocks using a wear-leveling strategy based on allocation requests and wear records. Experiments show that the proposed Tnvmalloc provides more than 10 times improvement in wear-leveling than typical allocators Glibc malloc, NVMalloc, and nvm_malloc, which becomes obvious especially in multi-Threaded scenarios. Moreover, when allocating large memory blocks, Tnvmalloc achieves three times faster than that of NVMalloc.

Original languageEnglish
Article number2250066
JournalJournal of Circuits, Systems and Computers
Volume31
Issue number4
Early online date2 Oct 2021
DOIs
Publication statusPublished - 15 Mar 2022
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2022 World Scientific Publishing Company.

Keywords

  • memory allocator
  • multi-Threaded friendly
  • NVMM
  • wear-leveling

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