Variance component analysis based fault diagnosis of multi-layer overlay lithography processes

Jie YU, S. Joe QIN*

*Corresponding author for this work

Research output: Journal PublicationsJournal Article (refereed)peer-review

29 Citations (Scopus)


The overlay lithography process is one of the most important steps in semiconductor manufacturing. This work attempts to solve a challenging problem in this technique, namely error source identification and diagnosis for multistage overlay processes. In this paper, a multistage state space model for the misalignment errors of the lithography process is developed and a general mixed linear input-output model is then formulated to incorporate both fixed and random effects. Furthermore, the minimum norm quadric unbiased estimation strategy is used to estimate the mean and variance components of potential fault sources, and their asymptotic distributions are used to test the hypothesis concerning the statistical significance of each potential fault. Based on the above procedures, the root cause of misalignment errors in a multi-layer overlay process can be detected and diagnosed with physical inference. A number of simulated examples are designed and tested to verify the validity of the presented approach in fault detection and diagnosis of multi-stepper overlay processes.
Original languageEnglish
Pages (from-to)764-775
Number of pages12
JournalIIE Transactions (Institute of Industrial Engineers)
Issue number9
Early online date30 Jun 2009
Publication statusPublished - 2009
Externally publishedYes


  • Error propagation
  • Misalignment error
  • Multistage fault diagnosis
  • Overlay lithography process
  • Semiconductor manufacturing
  • Variance component analysis


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